Nano-Scaled Fet Device For Cmos Technology

Author

Prabhat Ranjan Pathak, North Carolina Agricultural and Technical State University

Date of Award

2010

Document Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical Engineering

First Advisor

Walker, Dr. Alvernon

Abstract

In this work the 3-D structure of the Accumulation mode (ACM) and Enhance mode (ECM) FinFET was developed by the Taurus-Device Editor. The design of both ACM and ECM FinFET was optimized for high-performance IC applications to meet ITRS specification for I_off current, for 9nm gate length. The design of ACM and ECM FinFET is optimized, analyzed and compared against each other with respect to Darin Induced Barrier Lower (DIBL), Sub-threshold Swing(SS), operation and performance characteristics with varying electrical and physical parameters Silicon thickness (T_si), Source/Drain doping gradient (σ_sd), electrical channel length (L_eff ), lacer spacer width (L_sp) and Source/Drain Contact Resistance (r_sd). Finally, both designs were optimized for 9nm gate length for on current (I_on) to meet ITRS specifications for I_off. The simulation solves and includes Poisson, drift-diffusion transport equation and 3D-Schrodinger equation self-consistently.

Recommended Citation

Pathak, Prabhat Ranjan, "Nano-Scaled Fet Device For Cmos Technology" (2010). Dissertations. 134.
https://digital.library.ncat.edu/dissertations/134