Date of Award

2012

Document Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical Engineering

First Advisor

Iyer, Shanthi

Abstract

Thin film transistors (TFTs) were fabricated with a transparent amorphous gallium tin zinc oxide (GSZO) channel layer. GSZO is a promising, low cost replacement for the commonly used indium gallium zinc oxide (IGZO).The transistors were fabricated on Si substrates to optimize performance prior to transferring device production to flexible substrates. This dissertation will address the effects of deposition and post-deposition parameters on the film properties and interface traps. It will also address the parameters’ resultant effects on device performance and stability with the use of various characterization techniques. Film properties were studied using x-ray diffraction (XRD) and transmission measurements to assess the structural and optical properties of the deposited films. X-ray photoelectron spectroscopy (XPS) analysis was performed to determine the surface composition of the channel layer, and correlate the surface properties to the resulting device performance. Enhancement and depletion mode devices were fabricated. TFT performance was evaluated through the current-voltage (I-V) characteristics of the devices under normal, electrically stressed and photo-excited conditions operating conditions. Depletion mode TFTs were produced with drain current (ID)= 10-6 A, threshold voltage (VT)= -3 V, subthreshold swing (SS)= 1.3 V/decade, and on/off current ratio (Ion/off)= 106 when operated in the dark without gate stress. TFTs with 10 sccm oxygen incorporation during deposited and post-deposition annealing at 250 °C exhibits the best performance amongst enhancement mode devices with ID of 10-7A, VT of 3 V SS of 1.33 V / decade, and Ion/off of 106. In addition, a stable RT deposited TFT has been achieved with 2 sccm oxygen incorporation, and 250 °C post deposition annealing temperature, that exhibits a ΔVT as low as ~0.5 V for a 3 hour stress period under a gate bias of 1.2 and 12 V.

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